
This project shows a possible usage of start and stop events.

The timer in the SCT is configured in split mode (2 x 16-bit timers) 

Each half of the timer generates start and stop events, which alternatively starts and stops the other side of the state machine,
in a ping-pong like fashion.

Note: for keeping one timer in stopped state while exiting reset, the HALT bit needs to be cleared in the same write cycle as the the STOP bit.